DRAM systems provide low-cost data storage solutions because of the simplicity of their construction. Essentially, DRAM cells are made up of a switch or transistor, coupled to a capacitor. FIG. 1 illustrates a conventional DRAM cell 100 comprising transistor 106 and capacitor 108. Transistor 106 is turned on when word line 102 is activated, and the voltage (high/low) on bit line 104 is transferred to capacitor 108, causing capacitor 108 to store corresponding information (logic “1”/logic “0”, respectively). DRAM systems are organized as DRAM arrays comprising DRAM cells such as DRAM cell 100 organized in rows and columns. As can be appreciated, given the simplicity of DRAM cells, the construction of DRAM systems incurs low cost and high density integration of DRAM arrays is possible. However, because capacitors are leaky, the charge stored in capacitor 108 needs to be periodically refreshed in order to correctly retain the information stored therein.
Conventional refresh operations involve reading out each DRAM cell (e.g., row by row) in a DRAM array and immediately writing back the data read out to the corresponding DRAM cells without modification, with the intent of preserving the information stored therein. Accordingly, the refresh operations consume power. Depending on specific implementations of DRAM systems (e.g., double data rate (DDR), low power DDR (LPDDR), etc., as known in the art) a minimum refresh frequency is defined, wherein if a DRAM cell is not refreshed at a frequency that is at least the minimum refresh frequency, then the likelihood of information stored therein becoming corrupted increases. If the DRAM cells are accessed for memory access operations such as read or write operations, the accessed DRAM cells are refreshed as part of performing the memory access operations. To ensure that the DRAM cells are being refreshed at least at a rate which satisfies the minimum refresh frequency even when the DRAM cells are not being accessed for memory access operations, various dedicated refresh mechanisms may be provided for DRAM systems.
One refresh mechanism known in the art is referred to as an auto-refresh. A DRAM controller (e.g., a DDR controller, as known in the art for DDR systems) manages refresh operations in an auto-refresh state. The DRAM controller may direct a refresh command to be issued to the DRAM system at a specified refresh rate in the auto-refresh state.
Another refresh mechanism known in the art is referred to as a self-refresh, which may be internally managed by the DRAM system. A self-refresh state may be entered in a low power state of the DRAM system, such as an idle or standby state. In the self-refresh state, each row of a DRAM array may be taken through a sequence of read out and write back, over the course of a refresh cycle.
If memory access commands for performing memory access operations on the DRAM cells are received by a DRAM system while the DRAM system is in the low power state, the DRAM system may be taken out of the low power state into an active mode in order to service the memory access operations. This may entail exiting the self-refresh and entering the auto-refresh state. In conventional systems, transitioning from the self-refresh state to an auto-refresh state may also entail executing an additional refresh command to perform an additional refresh operation before exiting the self-refresh state, with an objective of ensuring that the minimum refresh frequency has been met before the transition takes place. As can be appreciated, power consumption by the DRAM system increases when the DRAM system is taken out of the low power state to an active state; and the additional refresh command adds to the increased power consumption.
Some DRAM applications may involve accesses to the DRAM cells for short durations of time while the DRAM system is in a low power state such as idle or standby. For example, in some wireless communication systems, a mobile phone may be required to periodically ping a base station or a cell phone tower even when the mobile phone is in a standby mode. Each ping may involve accessing a DRAM system in the mobile phone for a short duration of time. Conventional methods of accessing the DRAM system for each ping may entail exiting the low power state of the DRAM system and entering an active state. Thus, each ping can consume significant power.
There is an ever-increasing need for reducing power consumption of computing devices, particularly battery-operated handheld devices such as mobile phones, tablets, laptops, etc. Thus, there is also a corresponding need in the art for reducing the power consumption of DRAM systems.